Normal and random mismatch, between field effect transistors (FET), in standard complementary metal-oxide semiconductor (CMOS) manufacturing, decreases the accuracy of ADCs whose precision depend on matching of such FETs. Manufacturing costs are higher for ADCs that require high precision and highly matched passive components such as resistors and capacitor. Costs are also higher for those ADCs that need post fabrication trimming or on-chip calibration of FETs or passive components to attain higher accuracies. Resistor free, capacitor free, trim or calibration free, and clock free ADCs that rely on FET matching for their accuracy, generally yield lower precision and lower resolutions. Emerging green and low power applications require ADCs that operate at low voltage power supplies and low currents. Additionally, operating with low voltage power supplies generally restricts the input range of ADCs, which can limit ADC's accuracy over the full zero-scale to full-scale input signal span and constrain ADC's signal to noise ratio requirements. Operating at low currents also slows the conversion speed of ADCs. Sampling ADCs that for example utilize switching techniques, such as switch capacitors, can yield high accuracy ADCs, but they are more expensive due to the needed capacitors and exhibit higher dynamic power consumption because of the needed free running clock requirement.